1. Field of the Invention
The present invention relates in general to a semiconductor structure and its fabrication method, and, more particularly, to a die seal structure around a chip die for preventing the internal circuit of the chip die from the lateral stress induced during the period of cutting wafers, and its fabrication method.
2. Description of the Related Art
In the semiconductor process, a plurality of dies, each of which contains an integrated circuit, are fabricated on a semiconductor wafer at a time. Scribe lines are provided between every two adjacent dies so that the dies can be separated by cutting the semiconductor wafer along these scribe lines.
However, when a wafer is cut into a plurality of dies, lateral stress is induced, thereby affecting the internal circuits via the structure of the IC. Consequently, microcracking may occur and further affect the production yield. One approach for solving such a problem is to form a die seal structure between the scribe line and the peripheral region of the internal circuit. Therefore, stress induced by cutting wafers is generally blocked by the die seal and will not directly impact the internal circuit of a die. FIG. 1 shows a top view of a chip die. The die seal is directed to the structure between internal circuit 10 and scribe line 50. The die seal structure comprises buffer area 20, seal ring 30 and buffer space 40. Seal ring 30, which is a stacked structure comprising metal layers and dielectric layers, is usually formed together with the multi-metal interconnection process.
FIG. 2 (PRIOR ART) and FIG. 3 (PRIOR ART) illustrate two cross-sectional views of the conventional die seal structures, respectively. It is noticed that the die seal structures shown in FIG. 2 and FIG. 3 are formed together with a triple-metal interconnection process. Now referring to FIG. 2, the whole structure is formed on silicon substrate 4. Field oxide 12 is used as an isolation structure and also can be used to separate a die seal structure (comprising buffer area 20, seal ring 30 and buffer space 40) and internal circuit 10. Seal ring 30 comprises three dielectric layers 14, 16 and 18, wherein dielectric layer 16 is formed over dielectric layer 14, and dielectric layer 18 is formed over dielectric layer 16. Each of dielectric layers 14, 16 and 18 is covered with metal layers 15, 17 and 19, respectively, which are formed together with the triple-metal process. Finally, passivation layer 22 is formed and covers all the dielectric layers and the metal layers. In summary, seal ring 30 of conventional die seal structure shown in FIG. 2 is produced by alternately depositing the dielectric layers and the metal layers. It should be noted that these dielectric layers and metal layers are formed during the common semiconductor process and do not require extra steps. In general, seal ring 30 has a width of about 20 .mu.m, buffer area 20 between internal circuit 10 and seal ring 30 has a width of about 25 .mu.m, and buffer space 40 between seal ring 30 and the scribe line has a width of about 3.about.50 .mu.m.
The die seal structure shown in FIG. 3 is quite similar to that shown in FIG. 2, except in the following aspects. In FIG. 3, seal ring 30 includes three metal layers 32, 34 and 36, as in FIG. 2, and further includes metal plugs 31, 33 and 35, located between these metal layers. In this seal ring structure, metal layers 32, 34 and 36 and metal plugs 31, 33, 35 are also formed during the common metalization and plug-in process and do not require extra steps. Therefore, metal plugs 31, 33 and 35 are usually made of tungsten. Such a seal ring structrure is utilized in the die seal structure to enhance robustness to sawing stress, thereby preventing the internal circuit from damage.
In the development of process techniques, a technique called global planarization is commonly utilized. The most common one is CMP (chemical-mechanical polishing). When CMP is utilized in the fabrication process of semiconductors, the protection ability of the die seal may be reduced. The reason for this will be discussed in the following detailed description. When an inter-metal dielectric layer is planarized by using CMP, the dielectric layer between seal ring 30 and scribe line 50 may not be completely removed in the etching of the contact window, metal via, and passivation, and may accumulate continually on the buffer space. As shown in FIG. 2 and FIG. 3, dielectric material 24 on the buffer area 40 may have a depth of about 12000 .ANG. in the prior art. The residual dielectric material on buffer area 40 may be a path of stress when a wafer is sawed. Thereby, the reliability of dies may be reduced.
On the other hand, the stress can reach internal circuit 10 via dielectric material 24 and substrate 4. In the prior art, the die seal structure can not provide complete protection to internal circiuts.